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For many people who work in knowledge management, the numbers that describe the speed, size, and number of components of computer hardware have long since lost their meaning. If a number is already large (or small) beyond comprehension, making the number larger or smaller does not add to our understanding.
But, we use computers to write documents, find documents, and to access the Internet. Changes to computers, and in the Internet, will continue to change things we do every day.
Because computers have a great effect on our lives, our jobs, and our businesses, it is important to have some feel for the changes that occur in computes. Also, there is a very steady progression in these changes in computers. This steady rate of increase will help us in projecting that the changes we have personally seen in computers will continue at about the same rate for a considerable time into the future.
This white paper shows the statistics for Intel microprocessors that have been introduced over the past thirty years. The numbers are presented in a table so that a non-technical person can get a feel for the changes that have occurred over a period of three decades. In general, each of the statistics has increased by a factor of ten thousand. The processors are ten thousand times faster, the processors have ten thousand times as many transistors, and the transistors used to build the processors have shrunk in size by a factor of ten thousand (a factor of one hundred in each of the X and Y linear dimensions.)
In 1965 Gordon Moore, now Chairman Emeritus of Intel, observed that the capabilities of integrated circuits tended increase at a regular percentage rate per year. At the time, the number of transistors on an integrated circuit was doubling approximately every eighteen months. This regular percentage increase has come to be known as Moore’s law. It is described in great detail at: http://developer.intel.com/pressroom/archive/speeches/gem93097.htm.
The study of the History of Technology shows that when a given technology stops providing a regular percentage increase in capability each year, a new technology takes its place and continues to provide a regular increase in capability each year. An example is the rate of speed increase that continued when trains were replaced by airplanes as the fastest means of travel.
There are many examples of Moore’s Law, one of which is the increase in the capabilities of microprocessors shown in this white paper. (Please see below.) Others exist in fiber optics, magnetic disks, and nano-technology (see http://www.Foresight.org).
In document management, changes in computer technology have caused many system costs to decrease below the level of notice. For example, the cost to email a page is no longer a consideration. Many costs will soon drop below the level of notice, for example, the cost of delivering video over the Internet to desktops and into the home.
Some costs, such as providing access to useful information will never follow the decreasing costs of technology. This is because the integrity of a knowledge management system requires management by a person. The person ensures that the knowledge stored has been checked for accuracy, for quality.
However, to the extent that technology can eliminate the need for people to perform mechanical tasks, thus freeing people to spend time managing the quality of information, the decrease in the cost of technology can help to improve the quality of information on which business and personal decisions are based.
The end use of information is to make decisions. For good decisions, the information must be available and locatable, and the information must be correct.
Having a feel for changes that are occurring in computer technology can be valuable in planning the future of the use of information in many types of businesses and jobs in knowledge management.
Changes in computes affect different parts of the knowledge management industry to different degrees. Understanding the value of applying computing power to different jobs in knowledge management will help planners project the rate of change in each part of knowledge management.
Computers can contribute directly to the availability and locatability of information. Computers can contribute indirectly to the quality of information by freeing knowledge workers from mechanical tasks so that the knowledge workers can concentrate on managing the quality of the information being made available.
Computer technology should continue to contribute to rapid changes in knowledge management for a very long time to come.
Many physical systems have a limit to continuous growth. For example, in the United States, the number of persons using the Internet can only double one more time because one more doubling will bring the usage of the Internet to 100 percent of the population.
In 1997, about 100 thousand trillion transistors were manufactured, approximately one for each ant on the earth. [ http://www.intel.com/pressroom/archive/speeches/GEM93097.HTM "An Update on Moore’s Law", Intel Chairman Emeritus Gordon Moore]
The number of transistors manufactured is more than doubling each year at the present time. [Ibid]
In 2000 manufacturers are expected to ship 150 million PCs and 8 billion embedded microprocessors. [Intel's Computing Continuum Conference Explores Next 20 Years Of Computing, Dr. David Tennenhouse, San Francisco, CA, March 15, 2000, http://www.intel.com/pressroom/archive/releases/cn031500a.htm]
Intel dropped the ‘86’ designations for the ‘x86’ microprocessor line when Intel learned that the number ‘86’ could not be trademarked. The ‘Pentium’ followed the ‘486’, replacing the planned ‘5’ (with ‘Penta’, which means five in Greek,) in the ‘586’ designation.
Shrinking (or growing) in two dimensions can be illustrated by a checkerboard. If the checkerboard had 4 squares on each side instead of 8, the checkerboard would have a total of 16 squares instead of a total of 64 squares.
Thus, a doubling in each of the linear dimensions (edges of the checkerboard) leads to an increase by a factor of four in the number of squares on the checkerboard.
This relationship is also useful in calculating the number of boxes (records storage cartons) that can be stored in a room that has been doubled in size along all three dimensions (height, width, and depth.) This was known as the cube - square ratio in Gulliver’s Travels by Jonathan Swift (Lemuel Gulliver) (1726).
| Family | Trade Name (Code Name for Future Chips) | Clock Frequency in MegaHertz*** | Millions of Instructions per Second | Date of Introduction | Number of Transistors | Design Rule (Pixel Size) | Address Bus Bits |
|---|---|---|---|---|---|---|---|
| 80786 | (Northwood) | 3,000.0 MHz | TBA | 2003 | TBA | 0.13 micron | 64 bit |
| 80786 | (Madison) | TBA | TBA | 2003 | TBA | 0.13 micron | 64 bit |
| 80786 | (Deerfield)** | TBA | TBA | 2002Q2 | TBA | 0.13 micron | 64 bit |
| 80786 | (McKinley) | 1,000.0 MHz | TBA | 2001Q4 | TBA | 0.18 micron | 64 bit |
| 80786 | Itanium (Merced) | 800.0 MHz | TBA | 2000H2 | TBA | 0.18 micron | 64 bit |
| 80686 | (Willamette) | 1,500.0 MHz | *1,500.00 MIPS | 2000Q1 | TBA | 0.18 micron | 32 bit |
| 80686 | Pentium III | 1,000.0 MHz | *1,000.00 MIPS | March 1, 2000 | 28.1 million | 0.18 micron | 32 bit |
| 80686 | P III Xeon | 733.0 MHz | *733.00 MIPS | October 25, 1999 | 28.1 million | 0.18 micron | 32 bit |
| 80686 | Mobile P II | 400.0 MHz | *400.00 MIPS | June 14, 1999 | 27.4 million | 0.18 micron | 32 bit |
| 80686 | P III Xeon | 550.0 MHz | *550.00 MIPS | March 17, 1999 | 9.5 million | 0.25 micron | 32 bit |
| 80686 | Pentium III | 500.0 MHz | *500.00 MIPS | February 26, 1999 | 9.5 million | 0.25 micron | 32 bit |
| 80686 | P II Xeon | 400.0 MHz | *400.00 MIPS | June 29, 1998 | 7.5 million | 0.25 micron | 32 bit |
| 80686 | Pentium II | 333.0 MHz | *333.00 MIPS | January 26, 1998 | 7.5 million | 0.25 micron | 32 bit |
| 80686 | Pentium II | 300.0 MHz | *300.00 MIPS | May 7, 1997 | 7.5 million | 0.35 micron | 32 bit |
| 80586 | Pentium Pro | 200.0 MHz | *200.00 MIPS | November 1, 1995 | 5.5 million | 0.35 micron | 32 bit |
| 80586 | Pentium | 133.0 MHz | *133.00 MIPS | June 1995 | 3.3 million | 0.35 micron | 32 bit |
| 80586 | Pentium | 90.0 MHz | *90.00 MIPS | March 7, 1994 | 3.2 million | 0.60 micron | 32 bit |
| 80586 | Pentium | 60.0 MHz | *60.00 MIPS | March 22, 1993 | 3.1 million | 0.80 micron | 32 bit |
| 80486 | 80486 DX2 | 50.0 MHz | *50.00 MIPS | March 3, 1992 | 1.2 million | 0.80 micron | 32 bit |
| 80486 | 486 DX | 25.0 MHz | 20.00 MIPS | April 10, 1989 | 1.2 million | 1.00 micron | 32 bit |
| 80386 | 386 DX | 16.0 MHz | 5.00 MIPS | October 17, 1985 | 275,000 | 1.50 micron | 16 bit |
| 80286 | 80286 | 6.0 MHz | 0.90 MIPS | February 1982 | 134,000 | 1.50 micron | 16 bit |
| 8086 | 8086 | 5.0 MHz | 0.33 MIPS | June 8, 1978 | 29,000 | 3.00 micron | 16 bit |
| 8080 | 8080 | 2.0 MHz | 0.64 MIPS | April 1974 | 6,000 | 6.00 micron | 8 bit |
| 8008 | 8008 | .2 MHz | 0.06 MIPS | April 1972 | 3,500 | 10.00 micron | 8 bit |
| 4004 | 4004 | .1 MHz | 0.06 MIPS | November 15, 1971 | 2,300 | 10.00 micron | 4 bit |
|
* Approximately one instruction per processor clock cycle ** Itanium, formerly codenamed Merced, may be replaced by McKinley if further delayed. Deerfield is a low cost version of Madison. *** 1 KHz (KiloHertz) = 1 thousand cycles per second; 1 MegaHertz = 1 thousand KiloHertz; 100 KHz = .1 MHz, 1 GHz (GigaHertz) = 1 billion cycles per second; 1 GigaHertz = 1 thousand MegaHertz TBA To be announced http://www.esc-ca.com/processors/intel/future.htm (one source of data for future microprocessors) http://www.Intel.com/pressroom/kits/processors/quickref.htm (source of data for released microprocessors) |
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MHz: (MegaHertz) (Millions of processor cycles per second) The number of times the processor goes through one cycle. The start of a processor cycle is determined by a pulse (tick) from the processor’s clock.
GHz: (GigaHertz) (Billions of processors cycles per second). 1 thousand MHz = 1 GHz
1999 was the last year for PCs that had a speed measured in MHz. In 2000 GHz PCs were introduced and no one spoke of MHz PCs again.
MIPS: (Millions of Instructions per Second) with the introduction of the 80486 DX2, parallel instruction execution increased the number of instructions executed per processor cycle to approximately one instruction per cycle. Parallel instruction execution requires many more transistors, so the increase in the number of transistors has increased the number of instructions that can be executed per second faster than the clock cycle speed has increased. A larger transistor budget allows the addition of specialized instructions, which increase the microprocessor’s speed in processing specialized information such as graphics by increasing the amount of information processed per instruction.
GIPS: (GigaInstructions per Second) Billions of instructions per second. 1 thousand MIPS = 1 GIP
Design Rule: because the wires and components, including transistors, on chips are drawn photographically, the pixel size of the imaging process determines the width of the wires and the size of the transistors. The size of the transistors determines how many will fit on a chip of a given size. (The optimal size of a chip depends on the chip manufacturing processes. In general, chip size increases slowly over time.) The smaller the transistors, the more will fit on the chip, determining the chip’s transistor budget. The size of the transistors also determines the transistor’s switching speed. Smaller transistors switch faster. (One micron is one one-millionth of a meter or about 40 millionths of one inch. .1 micron, one-tenth of a micron, is one-ten-millionth of a meter or about 4 millionths of an inch.) Finally, the power required to switch smaller transistors is less, so smaller pixels in the design rules allow the batteries in laptop computers to last longer.
Number of Transistors: The number of transistors increases as the square of the decrease in design rule size. Each reduction in design rule size is chosen to about double the number of available transistors (the transistor budget). [For example: (.25 micron / .18 micron) x (.25 micron / .18 micron) = 2.] The gradual increase in die size (the size of the chip) also increases the number of transistors.
Address Bus Bits: The address bus width in bits is based on the microprocessor chip family. (In the later chips of the 80686 family, some changes have been made to make more memory addressable under special circumstances, by using 36 bits to address 16 times as much memory as is possible with 32 address bits, but the generalized addressing structure is still 32 bits.) Each time a bit is added to the address bus width, the amount of memory (RAM: Random Access Memory) that can be addressed is doubled. 4 bit addresses allow the addressing of 16 bytes of memory (and extra work is necessary to address 256 bytes of memory). 8 bits allow the addressing of 256 bytes of memory (and extra work is necessary to address 65,536 bytes of memory). 16 bits can address 65,536 bytes of memory (and extra work is necessary to address 640 KiloBytes of memory, as was the case on the early IBM PCs). 32 bits can address 4,294,967,296 bytes of memory (about 4 billion bytes). As memory prices drop, it becomes necessary to address over 4 billion bytes of memory. The 80786 family is due out from Intel in the year 2000. It will have a 64 bit address bus and will be able to address over 16 billion billion (16 quintillion) bytes of memory.
See also: http://www.intel.com/intel/intelis/museum/, Intel’s history of the microprocessor.
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Reprinted from Archive Planning, Volume 4, number 3, 2000, Archive Builders' analysis newsletter for document management. See http://www.ArchiveBuilders.com. All trademarks are the property of their respective holders.
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Steve Gilheany, BA in Computer Science, MBA, MLS Specialization in Information Science, CDIA (Certified Document Imaging System Architect), AIIM Master (MIT), and AIIM Laureate (LIT), of Information Technologies, CRM (Certified Records Manager, ARMA) has twenty years experience in document imaging and is a Sr. Systems Engineer at Archive Builders.
Steve Gilheany is a Sr. Systems Engineer at Archive Builders. He has worked in digital document management and document imaging for twenty years.
His experience in the application of document management and document imaging in industry includes: aerospace, banking, manufacturing, natural resources, petroleum refining, transportation, energy, federal, state, and local government, civil engineering, utilities, entertainment, commercial records centers, archives, non-profit development, education, and administrative, engineering, production, legal, and medical records management. At the same time, he has worked in product management for hypertext, for windows based user interface systems, for computer displays, for engineering drawing, letter size, microform, and color scanning, and for xerographic, photographic, newspaper, engineering drawing, and color printing.
In addition, he has nine years of experience in data center operations and database and computer communications systems design, programming, testing, and software configuration management. He has an MLS Specialization in Information Science and an MBA with a concentration in Computer and Information Systems from UCLA, a California Adult Education teaching credential, and a BA in Computer Science from the University of Wisconsin at Madison. His industry certifications include: the CDIA (Certified Document Imaging System Architect) and the AIIM Master (MIT), and AIIM Laureate (LIT), of Information Technologies (from AIIM International, the Association of Information and Image Management, http://www.AIIM.org, and the CRM (Certified Records Manager) (from the ICRM, the Institute of Certified Records Managers, an affiliate of ARMA International, the Association of Records Managers and Administrators, http://www.ARMA.org.
SteveGilheany@ArchiveBuilders.com Tel: +1 310-937-7000 Fax: +1 310-937-7001